Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Stratix IV and DDR2 - pin assignment problem?

Hello, i created a megafunction with the wizard for using the ddr2 memory on my stratix IV-board. But there seems to be a problem in the pin assignment. while place&route i get the followi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

In UniPHY the oct pins are called OCT_rup and OCT_rdn. This is what you need to connect your pin assignments to.

In your project they are connected to termination_blk0~_rup_pad etc. This is an AltmemPHY thing. Reassign these pins assignments to the correct pins.

I would delete all assignments and rerun the <>_pin_assignments.tcl file.