Stratix-3 DSP kit, Dual ADC usage

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The Stratix-III DSP kit contains 2 ADCs, 125MSPS and controlled using seperate clocks. I was thinking if it is possible to clock the ADCs 180 degrees out of phase with each other and double the sampling rate.

In other words, I would use a Minicircuits splitter to split one signal and feed it to each ADC. After sampling, I would reconstitute the signals.

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Have you tested the analog response of the individual ADCs? You'll want to do that first. You'd need to check that the board does not have an anti-aliasing filter built in (it probably doesn't, the Stratix II kit didn't). There's no point in doubling the clock rate if the ADC input bandwidth is only 60MHz.

At the end of this document is some testing I did on the SII DSP kit.

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf

Cheers,

Dave

Thanks for the quick reply Dave. It doesn't appear to have any filtering on the front end. In fact, they ship a 55MHz coaxial Minicircuits LPF to act as an external anti-aliasing filter.

I've seen the PDF you sent me, you're website has some great information and I actually had it bookmarked.

Aside from that, are there any other potential pitfalls you see going down this path?

Thanks

Matt

Hi Matt,

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It doesn't appear to have any filtering on the front end. In fact, they ship a 55MHz coaxial Minicircuits LPF to act as an external anti-aliasing filter.

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Ok, same as the SII DSP kit then.

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I've seen the PDF you sent me, you're website has some great information and I actually had it bookmarked.

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Great, glad it has helped.

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Aside from that, are there any other potential pitfalls you see going down this path?

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It should work fine. The potential trouble spots are; phase and amplitude imbalance, i.e., if you put exactly the same signal through each input, you'll get a slightly difference answer, and those slight differences will limit the dynamic range.

I'd start by putting exactly the same signal into both inputs, eg. a sinusoid, or perhaps the digital noise I show in the doc I referenced. Then look at three things; the power spectrum of each input, and then the cross-power spectrum of the two inputs (you cross-correlate them). In the noise source test, the cross-correlation phase should be dead flat if the signals are perfectly time aligned. If there is a phase slope, then there is a clock phase difference. This is ok if the slope is linear. Its the non-linearities in the slope that are the ones that will cause you issues. The amplitude of the three signals should be identical; if they are not, then that is the amplitude imbalance. Grab some data from the board and look at it in MATLAB. Simulate some data and put different amplitude errors in the even and odd samples and see what happens (look at the Nyquist channel).

At 125MHz clock rate, you should be fine.

Cheers,

Dave

while it would be a fun project, i can't help but think designing an HSMC card with the ADC you actually want is a better solution

that or design a HSMC to FMC gasket