Stratix 10M PCIe HIP clarifications

Hie,

My apologies for the delayed first response. Please check my replies to your questions below:

Question:

We want to use BAR0 to transfer our IP's CSRs from the host to the FPGA. It seems like with the internally-instantiated descriptor, this is not possible. Is this the case? Currently our existing design (on another vendor's chip) supports this use-case.

Answer:

Yes, your understanding is correct. Because of the Descriptor Controller Slave (DCS) is accessed through BAR0; hence the BAR 0 cannot be used to access any other slave interface when Internal Descriptor is selected. Currently, there is no workaround to use BAR0 to access CSR when using Internal Descriptor. The only option available is when Descriptor Controller is Externally Instantiated.

Question:

What is the difference between the HPTXS and the RD_DMA/WR_DMA master interfaces? I understand that one is the Avalon slave, and one is the master, but it seems like they do pretty much the same thing?

Answer:

Yes, the function is similar to send and fetch data between FPGA and host. However, RD_DMA / WR_DMA transfers at higher throughput compared to HPTXS. Hence, HPTXS is targetted for low bandwidth applications.

General question: Our IP has a slave interface (for CSRs) and a master interface (for external bus/memory accesses). What is the best way to connect our IP to the PCIe HIP? In the other vendor's toolflow, we just had to connect our IP's slave to the PCIe IP master, and our IP's master to the PCIe slave. It seems much more complicated in the Altera flow.

Yes, Stratix 10 PCIe AVMM IP design flow is not as simple as connecting the IPs slave to PCIe IP master and vice versa.

Please generate the Example Design for the Stratix 10 PCIe AVMM IP with your selected configuration to check the interface connection.

Do let me know if you have further questions.

Regards,

Nathan

Hi Nathan,

I appreciate the response. Eventually, I was able to connect the PCIe master (rxm_bar0) and slave (hptxs) interfaces to my IP with no issues. We are mostly using the FPGA to accelerate our verification process for an ASIC product so the lower throughput is not a huge concern -- yet.

Can you comment on the speed differential between the DMA and HPTXS interfaces? The IP's memory access pattern is comprised of a lot of small-ish (between 4 and 16 256b words) bursts throughout the runtime, so that may affect the data transfer speeds.

My apologies Ted, but I do not have the data in terms of speed difference between DMA and HPSTXS. I am also unable to derive any course estimate based on calculation. Hence, the only way to check this is to measure the throughput.

Regards,

Nathan