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User1573261788318367's avatar
User1573261788318367
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6 years ago

Stratix 10M PCIe HIP clarifications

Hi, I am going along with the guide here: https://www.intel.com/content/www/us/en/programmable/documentation/sia1468880988286.html and have some questions about how the HIP works. We want to use B...
User1573261788318367's avatar
User1573261788318367
Icon for New Contributor rankNew Contributor
6 years ago

Hi Nathan,

I appreciate the response. Eventually, I was able to connect the PCIe master (rxm_bar0) and slave (hptxs) interfaces to my IP with no issues. We are mostly using the FPGA to accelerate our verification process for an ASIC product so the lower throughput is not a huge concern -- yet.

Can you comment on the speed differential between the DMA and HPTXS interfaces? The IP's memory access pattern is comprised of a lot of small-ish (between 4 and 16 256b words) bursts throughout the runtime, so that may affect the data transfer speeds.