Forum Discussion

User1573261788318367's avatar
User1573261788318367
Icon for New Contributor rankNew Contributor
6 years ago

Stratix 10M DIB timing constraints

Hi all, I have a 20 MHz DUT clock and 400 MHz DIB clock in my design (split across the U1 and U2 dies of the Stratix 10M). In the timing report I"m seeing a lot of violations between these two domai...
User1573261788318367's avatar
User1573261788318367
Icon for New Contributor rankNew Contributor
6 years ago

Hi KennyT,

It is not a testbench. This is a special-purpose IP that's connected to the Stratix 10 PCIe HIP. Our design is spread across both dies of the Stratix 10M FPGA, and these dies talk to each other through the die-interconnect bridge ("DIB").

I posted this question specifically to ask about item 2c in your response. The DIB is an Intel-provided hard IP, and I don't know whether I can safely set false_path between the DUT clock and the DIB clock. The implementation of the DIB is a black box to me.