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User1573261788318367
New Contributor
New ContributorStratix 10M DIB timing constraints
Hi all, I have a 20 MHz DUT clock and 400 MHz DIB clock in my design (split across the U1 and U2 dies of the Stratix 10M). In the timing report I"m seeing a lot of violations between these two domai...
KennyT_altera
Super Contributor
Super ContributorDoes your DUT stand for test bench?
1) If yes, you do not need to include testbench to your design
2) If no, you may consider change your design to either
a) clock enable signal https://www.fpga4student.com/2017/08/how-to-generate-clock-enable-signal.html
b) add additional pipelines to close the timing.
c) set_multicycle_path
setting the false path means that you want the Quartus totally ignore those cross clock domain. I would not recommend it unless you are sure it won't break the functionality.
