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RPett4's avatar
RPett4
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Stratix 10 SERDES Reference clock Error(20445)

I am trying to utilize a LVDS SERDES IP block on the Stratix 10 SoC Development Kit. Per the development kit schematic, I have "HDMIREFCLK_P" driving my "inclock" port of the SERDES IP Block. When I try to build, I am getting the following error:

Error(20445): The reference clock on PLL "serdes_inst|lvds_0|core|arch_inst|pll_inst|internal_pll|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll", which feeds an LVDS SERDES IP instance, is not driven by a clock pin from an IO bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.

I can see from the pin planner that the HDMIREFCLK_P pin has been successfully mapped to PIN_AP9, which appears as a differential clock pair. All the serdes outputs are driving signals from the same bank (I/O Bank 4C), which are the HDMI_Lanes and HDMI_Lane_Clk.

Finally, the I/O Standard for the HDMIREFCLK_P is set to LVDS, and all other pins in the bank are either set to LVDS or "High Speed Differential I/O."

Can someone provide help?

1 Reply

  • SreekumarR_G_Intel's avatar
    SreekumarR_G_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Can you look at the bank connected to the clk input (which is PLL instantiated) and L:VDS bank which you plan to use both are same ?

    Other easy way is , if you remove the pin assignment from the assignment editor and build the same. Then you can see inclk of the PLL where it is default mapping by the quartus. I believe you will get idea from the bank where it is mapping.

    Thank you,

    Regards,

    Sree