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RPett4
Occasional Contributor
Occasional ContributorStratix 10 SERDES Reference clock Error(20445)
I am trying to utilize a LVDS SERDES IP block on the Stratix 10 SoC Development Kit. Per the development kit schematic, I have "HDMIREFCLK_P" driving my "inclock" port of the SERDES IP Block. When I ...
SreekumarR_G_Intel
Frequent Contributor
Frequent ContributorCan you look at the bank connected to the clk input (which is PLL instantiated) and L:VDS bank which you plan to use both are same ?
Other easy way is , if you remove the pin assignment from the assignment editor and build the same. Then you can see inclk of the PLL where it is default mapping by the quartus. I believe you will get idea from the bank where it is mapping.
Thank you,
Regards,
Sree
