Stratix 10 Phylite IP , deviation in data sampling at different groups(Input Path Signal)

Hi , Configuration detail: Problem Statement: For group 0 data is sampled correctly as expected but for group 1 data to core signal the data sampled internally by phylite is shif...

Memory

Farabi

Regular Contributor

6 months ago

Hello,

Bit [8:7] and bit [6:4] are used together to select DQ pins:

bit[8:4] = {2'h1, 3'h0} -> DQ0

bit[8:4] = {2'h1, 3'h1} -> DQ1

bit[8:4] = {2'h1, 3'h2} -> DQ2

bit[8:4] = {2'h1, 3'h3} -> DQ3

bit[8:4] = {2'h1, 3'h4} -> DQ4

bit[8:4] = {2'h1, 3'h5} -> DQ5

bit[8:4] = {2'h2, 3'h0} -> DQ6

bit[8:4] = {2'h2, 3'h1} -> DQ7

bit[8:4] = {2'h2, 3'h2} -> DQ8

bit[8:4] = {2'h2, 3'h3} -> DQ9

bit[8:4] = {2'h2, 3'h4} -> DQ10

bit[8:4] = {2'h2, 3'h5} -> DQ11

And about the abnormal behavior between groups, could you please run the simulation waveform showing the operation of all PHY Lite IP signals of both groups in one view.

So we can get the timing relationship of rdata_en, strobe_io, and rdata_valid of both groups in their testbench (and then check if there are any differences)

Could you please disable the dynamic reconfig in the IP and test again to see if the issue still happen?

regards,

Farabi