HBhat2
Contributor
6 years agoStratix 10 - Example design for dynamic reconfiguration
Hi,
I am using L-tile S-10 SoC dev kit and using native PHY IP for transceiver interface.
I want to switch the data rate between 10G and 20G using dynamic reconfiguration. Here, both Native PHY and ATX PLL must be reconfigured as the serial clock varies for targeted data rates. However, reference clock frequency remains same (156.25MHz).
Any example design is available for stratix 10 L-tile dynamic reconfiguration?
With regards,
HPB