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Altera_Forum's avatar
Altera_Forum
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16 years ago

strange CRA register map in PCIe ref design based on SOPC flow

Hi every one

I use PCIe soft IP based on the sopc flow. I obversed that in the testbench altpcietb_bfm_driver.v the DMA CRA register map are strange.

To access DMA read addr register,write addr register ,length register and control register,the testbench write addr are CRA base + 0x08, CRA base + 0x10,CRA base + 0x18,CRA base+ 0x30.

The CRA access is through bar 2 which is 32 bit non-prefetch bar. Why the write addresses are not CRA base + 0x04, CRA base + 0x08,CRA base + 0x0C,CRA base + 0x18?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks for reply.

    My avalon-MM custom component's control interface is 32bit width(the readdata and writedata signals are 32 bit).

    I connect the component's control interface with BAR 2 and want to access register in the control interface from root complex. Should the address increase with regOFFSET *8 ? or regOFFSET *4 ?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    If you do a 64-bit write at address 0 of BAR0, will be done 2 writes at offsets 0 and 1. It's possible to do a 32-bit write, so, will be done one write at respective offset.

    This question is a little confused to understand. Take a look on the section Address Alignment of chapter Avalon Memory-Mapped Interfaces of the document Avalon Interface Specifications to try understand this question.

    I recommend to look the signals with a signaltap module, and try to understand the address alignment.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    If you do a 64-bit write at address 0 of BAR0, will be done 2 writes at offsets 0 and 1. It's possible to do a 32-bit write, so, will be done one write at respective offset.

    This question is a little confused to understand. Take a look on the section Address Alignment of chapter Avalon Memory-Mapped Interfaces of the document Avalon Interface Specifications to try understand this question.

    I recommend to look the signals with a signaltap module, and try to understand the address alignment.

    --- Quote End ---

    Thanks for help.

    Thourgh the pcie user guide give a sopc based example,it does not say that the 64 bit prefetch BAR 1:0 and 32 bit pretch Bar 2 are 64 bit interface explicitly. I found that when i generated the sopc system the builder give a warning stated that 64 bit prefetch BAR 1:0 only support 64 bit memory.

    To connect my 32 bit custom component control interface to Bar 2, as you say,64 bit write to Bar 2 will be done 2 writes.So I recoded the 32 bit registers with address (byte offset) 0x0,0x8,010,.... It works correctly.

    Thanks again.