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Altera_Forum
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15 years ago

State Machine Editor with DSP Builder- HDL file not generated

Hi, I'm using the Graphical State Machine Editor with DSP Builder and I noticed that after specifying my state machine and closing the state machine editor window that the inputs and outputs d...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Hi, I'm using quartus version13.0 and want to verify whether the state machine is correct with the HDL code I have written and/or vice versa . However, I can't get HDL file generated after specifying a simple state machine using a State Machine editor. Vice versa, I also can't get to view the state machine from Verilog HDL code that I have written. Appreciate if anyone can help.