Forum Discussion
New ContributorSSGDMA Bursting Manager Interface BAR
Hi @jc_ddc ,
I check internally, unfortunately we do not have any well proven 100% design to reduce the resource utilization for MCDMA.
For effective working mcdma , I would strongly suggest to consider Agilex5 Modular devkit or Premium devkit.
Else you can try to start by minimizing the number of channels and FIFO depths in the MCDMA configurator. If that's insufficient, consider a simpler DMA IP or a custom solution if your resource constraints are very tight.
Regards,Wincent_Altera
New ContributorHi Wincent,
Thanks for your reply! I'm basing resource utilization off what's described on the resource utilization page of the MCMDA datasheet: https://www.intel.com/content/www/us/en/docs/programmable/847470/25-1-1/resource-utilization.html.
The FPGA being used is the A5E013A, which only has 358 M20Ks available and a PCIe 4 x4 interface. Based off the resource utilization for the MCDMA, it seems we'd be unable to use with this part.
Do you have any suggestions on how resource utilization for the MCDMA IP may be decreased?
Thank you!
Regular ContributorHi @jc_ddc ,
I check internally, unfortunately we do not have any well proven 100% design to reduce the resource utilization for MCDMA.
For effective working mcdma , I would strongly suggest to consider Agilex5 Modular devkit or Premium devkit.
Else you can try to start by minimizing the number of channels and FIFO depths in the MCDMA configurator. If that's insufficient, consider a simpler DMA IP or a custom solution if your resource constraints are very tight.
Regards,
Wincent_Altera
