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jc_ddc's avatar
jc_ddc
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3 months ago
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SSGDMA Bursting Manager Interface BAR

Hello, I am working on a PCIe interface for an Altera Agilex 5 device. The PCIe interface will have two BARs defined for accessing user memory and registers without DMA (ex. memory mapped to BAR 1, ...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 months ago

    Hi @jc_ddc ,

    I check internally, unfortunately we do not have any well proven 100% design to reduce the resource utilization for MCDMA.
    For effective working mcdma , I would strongly suggest to consider Agilex5 Modular devkit or Premium devkit.

    Else you can try to start by minimizing the number of channels and FIFO depths in the MCDMA configurator. If that's insufficient, consider a simpler DMA IP or a custom solution if your resource constraints are very tight.

    Regards,

    Wincent_Altera

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 months ago

Hi @jc_ddc ,

Yes, the BAM is mapped to BAR1 accordingly to the user guide



However, the MCDMA resource utilization exceeds that of the FPGA used for this design (it uses way more M20Ks than available).
>> Which OPN that you are using, if you are using the devkit according to the design example, by right you wont observed this problem.
>> IF you need to use your custom OPN , you may try to optimize the design memory utilization
>> https://www.intel.com/content/www/us/en/docs/programmable/683174/25-1/memory-optimization-m20k-mlab.htmlhttps://www.intel.com/content/www/us/en/docs/programmable/683174/23-3/memory-optimization-m20k-mlab.html

Regards,
Wincent

  • jc_ddc's avatar
    jc_ddc
    Icon for New Contributor rankNew Contributor
    3 months ago

    Hi Wincent,

    Thanks for your reply! I'm basing resource utilization off what's described on the resource utilization page of the MCMDA datasheet: https://www.intel.com/content/www/us/en/docs/programmable/847470/25-1-1/resource-utilization.html.

    The FPGA being used is the A5E013A, which only has 358 M20Ks available and a PCIe 4 x4 interface. Based off the resource utilization for the MCDMA, it seems we'd be unable to use with this part.

    Do you have any suggestions on how resource utilization for the MCDMA IP may be decreased?

    Thank you!

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      3 months ago

      Hi @jc_ddc ,

      I check internally, unfortunately we do not have any well proven 100% design to reduce the resource utilization for MCDMA.
      For effective working mcdma , I would strongly suggest to consider Agilex5 Modular devkit or Premium devkit.

      Else you can try to start by minimizing the number of channels and FIFO depths in the MCDMA configurator. If that's insufficient, consider a simpler DMA IP or a custom solution if your resource constraints are very tight.

      Regards,

      Wincent_Altera