Jo910
New Contributor
5 years agoSPI-to-Avalon-Bridge answers always IDLE
Hi,
i try to implement a SPI-to-Avalon-Master-Bridge together with an On-Chip-Flash on a MAX10. I connected both in QSYS and started a simulation. Unfortunately the Bridge always answers with "IDLE" (0x4A). By using the Intel documents I searched out the following bytes in order to read status register (address 0x0000_0000) of the On-Chip-Flash:
0x7A, 0x7C, 0x00, 0x10, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7B, 0x00
Do I have to start transmitting with 0x7A (from left to right)? --> 01111010 (from left to right)
Can nss be low during the complete transaction or has nss to be deactivated after each byte?
Is there something else, I have to watch out?
Thank you.