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Re: SPI-to-Avalon-Bridge answers always IDLE
Hi, I already found section 4 and figure 6 in the documents, but figure 6 only shows a transaction including 1 byte. I don't know exactly how to write a complete transaction. What byte and what bit has to be sent first? I want to simulate a read operation at avalon adress 0x0000 0000 (that should be status register of the On-Chip-Flash) with Modelsim. After reading the documents, I think I have to sent the following bytes: 0x7A, 0x7C, 0x00, 0x10, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7B, 0x00 But the IP Core always answers with IDLE (that means that there is no data to send). Could you help me modifying my modelsim script attached in order to run my read operation? Thank you.1.2KViews0likes1CommentSPI-to-Avalon-Bridge answers always IDLE
Hi, i try to implement a SPI-to-Avalon-Master-Bridge together with an On-Chip-Flash on a MAX10. I connected both in QSYS and started a simulation. Unfortunately the Bridge always answers with "IDLE" (0x4A). By using the Intel documents I searched out the following bytes in order to read status register (address 0x0000_0000) of the On-Chip-Flash: 0x7A, 0x7C, 0x00, 0x10, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7B, 0x00 Do I have to start transmitting with 0x7A (from left to right)? --> 01111010 (from left to right) Can nss be low during the complete transaction or has nss to be deactivated after each byte? Is there something else, I have to watch out? Thank you.1.2KViews0likes3CommentsMAX10: JTAG ISP
I plan to use a MAX 10M02SCE144I7G FPGA on my next PCB. FPGA code will be generated by Quartus. I know how to programm FPGA by using external JTAG header, but I want to programm FPGA with a Microprocessor via ISP. Is there another possibility to programm FPGA without using JTAG? What solution whould be the easiest way to implement a ISP for MAX 10 connected with a Microprocessor?711Views0likes1Comment