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Jo910's avatar
Jo910
Icon for New Contributor rankNew Contributor
5 years ago

SPI-to-Avalon-Bridge answers always IDLE

Hi, i try to implement a SPI-to-Avalon-Master-Bridge together with an On-Chip-Flash on a MAX10. I connected both in QSYS and started a simulation. Unfortunately the Bridge always answers with "IDLE...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

You may checkout the section 4. Avalon-ST Serial Peripheral Interface Core.

The Avalon-ST SPI core waits for the nSS signal to be asserted low, signifying that the SPI master is initiating a transaction. The core then starts shifting in bits from the input signal mosi.

Thus, the nss need to be low during the complete transaction.