SPI Synchronization Problem

OK.

I can't remember the details of SPI but is the receive data sampled on the rising or falling edge of the clock?

If it is the rising then you may have setup/hold times if the data changes very close to the sampling clock edge. It might be worth seeing if you can ensure the receive data is sampled on the falling edge of the clock.

I apologize if this cannot be done on the Altera core or your Atmel part but I am a bit rusty with SPI

Rgds

Vern