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Altera_Forum
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15 years ago

Source of errors in data from SGDMA

Hello, Sorry to be back so quick but I have spent the last two days on this and am at a loss. I have an SGDMA which is reading 16 bit data from an 8bit SDRAM and streaming this to a vide...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

It may depend on the output delay that you stated for the clk pin. Try to put a longer one.

But as long as all your I/O timing requirements are made relative to the clock pin, it shouldn't be a problem.

At 70MHz SDR I think that Quartus is able to make you meet the timing requirements without requiring a phase shift. If you get negative slack on the I/O again, you can try and adjust the shift until you don't.