Source of errors in data from SGDMA

Hi Daixiwen,

Though there is a VREF pin used within the data bus that capture was on a DIFFIO pin; I have monitored a couple more data bits and the waveforms are practically identical.

I am not sure how to tell if it is the scope or not as I only have one type of probe, the rise time of the clock signal however doesn't seem to be affected. (Though that is a PLL output)

Until now I was using the Classic Timing Analyzer. It reports the rise time of 0.9ns, for both the clock and the data bus pins.

I am taking one of the online tutorial/courses from Altera on TimingQuest and will try and use this to assess the design.