Source of errors in data from SGDMA

There doesn't seem to be anything wrong with the memory transfers done by the DMA. You should only look at the data on the m_read interface when readdatavalid is 1. When that signal is 0 the data could be anything.

So the problem could rather come from the data written by the Nios CPU to the memory, or a problem on the memory controller when it uses bursts. Could you do a setup with a Nios CPU that has a data cache (with bursts enabled) and run a memory test application from on-chip memory? This setup should test the burst operation of the DRAM controller.