Source of errors in data from SGDMA

Here are some captures showing the readdatavaliad and other control signals for the SGDMA interfaces.

The m_read_read signal has an interesting pattern when comparing it with the spurious high bits which I assume make up the white lines, though not 100% consistent, but the random dropped bits still appear to be just that.

I am using the 'On-Chip FIFO Memory v9.1' from the SOPC builder (as opposed to the Avalon-ST Dual Clock FIFO and Avalon-ST Shared Memory FIFO).