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Altera_Forum
Honored Contributor
Honored ContributorSource of errors in data from SGDMA
Hello, Sorry to be back so quick but I have spent the last two days on this and am at a loss. I have an SGDMA which is reading 16 bit data from an 8bit SDRAM and streaming this to a vide...
Altera_ForumHonored Contributor
Honored ContributorHere are some captures showing the readdatavaliad and other control signals for the SGDMA interfaces.
The m_read_read signal has an interesting pattern when comparing it with the spurious high bits which I assume make up the white lines, though not 100% consistent, but the random dropped bits still appear to be just that. I am using the 'On-Chip FIFO Memory v9.1' from the SOPC builder (as opposed to the Avalon-ST Dual Clock FIFO and Avalon-ST Shared Memory FIFO).
