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Altera_Forum
Honored Contributor
15 years agoHi Daixiwen,
Thank you for looking at this. Sorry I didn't realise this forum would allow me to attach the images. Do those show everything you need? The Ready/Valid looks about right if I query the FIFO fill level in software it oscillates around 8185-8190 as expected. Bursting is enabled with a max count of 8 on the data, no bursting on the descriptors (these have their own dedicated on-chip memory).