SOPC read latency question

Thanks very much for your reply. I have read the Avalon spec and I realize now that I used incorrect language in my question. In fact, I set up the slave with zero latency (no pipeline), zero write wait states and one read wait state. I don't know why there should be a read pipeline delay in this case. I have played around a bit more with the C code and it definitely does behave like the read has a pipeline delay of one. I have done an rtl simulation of the peripheral and it behaves as I expect. I do have the output registered and so I understand why I need the read wait state. But I don't understand where the pipeline delay is coming from.