SOPC read latency question

Hi,

When you set read latency in the Component Editor to 1, you are indeed creating a pipelined system where the next read can be issued before the data from the first read is returned. This is only an option for read cycles; write cycles cannot be pipelined.

You might try looking at the sample waveforms generated by the MegaWizard Plug-in manager (Documentation Button -> Generate Sample Waveforms) and comparing them to the Component Editor settings. If you are registering the output of the memory then you will have to wait an extra cycle.

I suggest reading http://www.altera.com/literature/manual/mnl_avalon_spec.pdf for the details on the timing options available when interfacing with an Avalon bus.

This is a hardware issue and should be dealt with in hardware. There may be workarounds such as issuing double reads to the same address and discarding the first one - but these are unreliable and unnecessary, since we have full control over the hardware timing.