New ContributorI want to use SDRAM Controller IP in Quartus 23.1std, but I found that Quartus 23.1std does not support this IP.
I also did not find a similar or new version of SDRAM Controller in Intel FPGA Intellectual Property. How can I control SDRAM in Quartus 23.1std? Or is there any recommended related IP that can help me?
Super ContributorWhat FPGA are you targeting? What memory do you want to access?
New ContributorI don't quite understand what you mean? I want to control its SDRAM in DE10-STANDARD
Super ContributorWell you didn't mention that you were using a dev kit.
So it's a Cyclone V: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=1046&PartNo=2#contents
The SDRAM is DDR3 and accessed via the HPS only, so you could create a Platform Designer system from scratch or use an example design from Terasic's resource page that would include the DDR3 IP: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=1046&PartNo=4#contents
Edit: whoops you mean this board: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=1081&PartNo=2#contents
But again, you can get an example design from the Resources page in the "CD" download: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=1081&PartNo=4#contents
New ContributorThank you. The DE10-STANDARD has 64MB SDRAM on the FPGA side and 1GB DDR3 on the HPS side. Now I want to control the SDRAM on the FPGA side.
In the example design, the SDRAM Controller IP is used in Quartus 16.1 to read and write access to the 64MB SDRAM on the FPGA side. However, this IP is no longer supported in Quartus 23.1. So I want to know if there are other IPs that can replace the SDRAM Controller IP?
New ContributorHello,
Unfortunately there isn't a SDRAM IP for Cyclone V in Quartus 23.1 std. Here are the memory IPs available (only DDR2, DDR3, and LPDDR2):
Thanks.
Super ContributorHi,
DE10-Standard comes with demonstration code, e.g. project DE10_Standard_DRAM_RTL_Test. I did two checks:
1. Compiled the project as is in Quartus 24.1 Std. Although upgrade of some 16.1 IP (FIFO, PLL) is suggested, it compiles without errors.
2. Performed Auto-Upgrade to 24.1 IP, no problems.
There are some warnings related to project .sdc resulting in unconstrained IO pathes, that should be handled, but the basic SDRAM code is working well. This is just expectable because SDRAM interface code uses other than DDR RAM no FPGA specific hardware resources and can be freely ported between FPGA series and Quartus versions.
Regards
Frank
