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Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- No if anything it should be: Simulink Input, In blocks (IO&bus), HDL Import -> HDL Input -> GPin, <datapath> , GPout -> HDL Output -> Out blocks (IO&bus) , Scope --- Quote End --- Cool, thanks!! That works perfectly!! I have just a curiosity how is Simulink able to run his functional simulation by using the HDL Import? I mean how is it able to interpret the VHDL code?