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You could route all the inputs to the state machine out of the advanced part of the design as outputs into state machine and then route the results back in. If the state machine is essentially in the middle of your datapath then this might cause problems if the signals go through the same ChannelIn/ChannelOut blocks as the main input/output of the system.
In this case you could try making the inputs/outputs go through GPIn/GPOut blocks although this can often lead to simulation mismatches in Modelsim.
Without seeing a design it's difficult to say anything more.
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Mmm ok, but right now I was just trying to run the FSM and it is not working showing the errors of my first post, I have from the lowest level of subsystem to the highest:
1- HDL Import block
2- HDL In/Outputs with Device block
3- In/Output ports (IO & bus) with simulink inputs + scope
And what about designing an FSM with the Advaced blockset, is that possible?
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