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Honored Contributor
Honored ContributorSoft ip core design
Hi, Basically i want to design one fifo soft ip core which should work any vendor FPGA.(I know so many fifo ip core's are there in market:-P). Already i designed fifo(256x8) using VHDL code and sa...
Altera_ForumHonored Contributor
Honored ContributorFWIW: Contrary to a statement in that document, if you do concurrent read and write to the same location with the same clock but without 'old data' configured you can get a mixture of the old and new values - you aren't guaranteed to see one or the other.
(OK - that was actually two clock mode with both clocks being the same...)
