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Altera_Forum
Honored Contributor
Honored ContributorSoft ip core design
Hi, Basically i want to design one fifo soft ip core which should work any vendor FPGA.(I know so many fifo ip core's are there in market:-P). Already i designed fifo(256x8) using VHDL code and sa...
Altera_ForumHonored Contributor
Honored ContributorThe problem will be subtle differences between architectures and tools. The problem with a "generic" fifo is that is will never take full advantage of the architecture of all chips. Usally the best way to get round this is to write a wrapper around the vendor IP with a generic called "CHIP_NAME" or something that then isntatiates the correct vendor IP. This way you can have a generic top level, with a nicely optimised design underneath.
