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Altera_Forum
Honored Contributor
Honored ContributorSoft ip core design
Hi, Basically i want to design one fifo soft ip core which should work any vendor FPGA.(I know so many fifo ip core's are there in market:-P). Already i designed fifo(256x8) using VHDL code and sa...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I don't think there is a safe way to synthesize a two port two clock ram. Pete --- Quote End --- This article suggests that you can, but I think there are slight differences in the templates that XST and Quartus expect so you can't have one generic description that will work with all (Altera/Xilinx) devices..... http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/ Nial
