Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSoft ip core design
Hi, Basically i want to design one fifo soft ip core which should work any vendor FPGA.(I know so many fifo ip core's are there in market:-P). Already i designed fifo(256x8) using VHDL code and sa...
Altera_ForumHonored Contributor
Honored ContributorA single clock fifo should be no problem. Simple pointers and synthesizable memory is all that is needed.
However when dealing with 2 clocks, several issues come into play. You can use Gray encoding to deal with the pointer issues, but I don't think there is a safe way to synthesize a two port two clock ram. Pete
