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Altera_Forum
Honored Contributor
Honored ContributorSlow PCIe cycles
I'm seeing very slow PCIe cycles from a PPC master to Altera FPGA Avalon MM slave peripherals. Typical times are 4us for a read and 7us for a write - which seem extremely pedestrian to me! Does...
Altera_ForumHonored Contributor
Honored ContributorPossibility to improve latency would be:
1) Increase the application clock frequency to 125MHz (if existing setting is only 62.5MHz). 2) Configure the core to higher speed. 3) Configure the core to wider lanes. Memory read is longer latency because it's compulsory to return the Completion packet.
