Honored Contributor
Honored ContributorOnce again thanks for your answer!
Actually my slave is another NIOS that is interfacing two Ethernet MACs and handling UDP communication. If a relevant packet arrived it is copied to the DPRAM using a DMA. The idea was to avoid another copy on the application side - eg in the attached sdram - and use the data in the dpram. So it boils down to inter-cpu communication mechanism. I have a whole control data block in the beginning of the dpram that handles this communcation - but little of it is really critical. I also considered the PIO alternative as a mean of async communication. I should run the PIOs in the same clock domain as the CPUs- not slower - otherwise I'll build a bottleneck?!? Will the PIO solution outperform a mutex based solution? I have that feeling that there's a nifty (and easy) solution for it by somehow juggling with the possible bit change states as you suggested above. I didn't quite get what you meant with that: --- Quote Start --- The Nios cpu reads tightly coupled memory every clock cycle, discarding the data if the instruction isn't a memory read or if the address doesn't match the memory block. If the instruction pipeline stalls (eg on an Avalon cycle) it needs to keep the data even though the address has been updated. On M9K this is done by deasserting clken (dual clock mode) or asserting 'address hold' (single clock mode). I don't know anything about DPRAM blocks. --- Quote End --- Can you point me to the documentation where this is elaborated? Thanks a lot!
