Simultaneous Write/Read to on chip dual port RAM

Thanks for the answer. This is the problem I'm trying to solve just now. How can a implement a mechanism that allows me to only process complete buffers. I thought about having a control structure in the DPRAM that manages a page flipping mechanism. But again within this control structure I could get corrupted data.

A avalon mutex could be used to handle this problem. I could also retreat to using a single port ram. In this case the avalon arbitration would handle the accesses - of course not being able to implement it as tightly coupled memory.

The CPU is basically performing closed-loop control tasks. The data in the dpram will for example contain the desired value for the controllers. This comes down to one acces per process variable per cycle. The target control frequency would be something around 3kHz. I can not judge how much in this case the performance would be in/decreased using tightly-coupled memory.

Thanks!