Simultaneous Write/Read to on chip dual port RAM

With M9K we got garbage - well the old or new value of each bit, not of the whole word.

The error rate varied by device and by build. Minor changes to the logic caused different chips to fail.

The Nios cpu reads tightly coupled memory every clock cycle, discarding the data if the instruction isn't a memory read or if the address doesn't match the memory block.

If the instruction pipeline stalls (eg on an Avalon cycle) it needs to keep the data even though the address has been updated. On M9K this is done by deasserting clken (dual clock mode) or asserting 'address hold' (single clock mode).

I don't know anything about DPRAM blocks.

However if you are filling in buffers using dma then you probably don't want to process a mixture of the old and new data for an entire buffer - so a corrupt byte in the middle of such a buffer won't be read anyway.

Using tightly coupled memory will give better performance, how significant it is depends rather on what your code is doing.