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Obviously simultaneous writes will cause problems.
In our case, one Avalon Master is reading while the other Master is writing.
So, the question is, will simultaneous write and read of the SAME address cause problems. It does not matter if I read "old" or "new" data as long as the write is successful and I don't read garbage or a combination of "old" and "new".
The Master that writes also uses other portions of the RAM and I'm hoping to avoid the arbitration delays with a single port RAM.
Thanks,
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What about (a) using a 2x faster clock for read and write but 1x clock for addressing (b) reading before writing. That way from the same address you first read and then write. Also (c) make the logic such that the enables for read and write are mutually exclusive i.e. when read is enabled, write is not and vice versa. That way, when the same address is on the bus, you can only do one of the two operations.
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