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TSchu3's avatar
TSchu3
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Simulating Triple Speed Ethernet, Decryption Fails

Hello, I am trying to simulate the TSE testbench IP generated with Quartus Prime Standard 18.0. My simulator is Cadence Xcelium. Xcelium cannot decrypt the TSE testbench submodules. I have not enco...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI Travis,

It's good to clarify the problem statement again.

  1. Now we are aligned that Cadence NCSIM or NCLaunch is the right sim tool to use
  2. Regarding your question on "Why are the Cadence submodules not generated and how can I get them ?"
  • This is the part that confused me. I used Quartus v19.1 standard edition to open up your earlier TSE QSYS design file, generate verilog sim model design files and I can see that cadence sim submodules design files are generated as per attached pic. These are cadence encrypted design files, not Mentor or Aldec
    • Are you saying you faced some issue in generating "cadence sim submodules design file ?" where you see different outcome as compare to my screenshot pic ? Can you show me your screen shot to highlight the issue to me ?
    • Or you managed to generate "cadence sim submodules design file" but faced problem compiling these design in Cadence NCSIM ? Then can you show me the error log ?

Thanks.

Regards,

dlim