Forum Discussion
Deshi_Intel
Regular Contributor
5 years agoHI,
- May I know which FPGA product that you are using here ?
- Can you share with me your TSE IP QSYS design file so that I know what setting that you are using in order to duplicate this sim issue ?
- May I know which Cadence Xcelium version that you use ? Based on TSE user guide, by right there should be another ./cadence or ./xcelium sim folder that you can use
- Also, have you try with latest Quartus version like Quartus Standard v19.1 to see if it helps to resolve issue ?
Thanks.
Regards,
dlim