Simulating the Generic Serial Flash Interface with ModelSim and Quartus 19.1

Hello,

I'm trying to simulate a component that interacts with the Generic Serial FLash Interface Intel IP. I have created a small QSYS system that only contains a clock source BFM, a reset source BFM, an Avalon-MM master BFM, the GSFI and the component to be tested.

I can compile the design without any errors.

When I start the simulation in ModeilSim I get the following error message:

** Error (suppressible): (vsim-3584) ./../modelsim/sim/../intel_generic_serial_flash_interface_if_ctrl_191/sim/flash_ctrl_tb_intel_generic_serial_flash_interface_if_ctrl_191_ztsk5pi.sv(860): Module parameter 'ENABLE_SIM_MODEL' not found for override.
# Time: 0 ps Iteration: 0 Instance: /test_program/flash_ctrl_tb_inst/intel_generic_serial_flash_interface_top_0/qspi_inf_inst File: ./../modelsim/sim/../intel_generic_serial_flash_interface_if_ctrl_191/sim/flash_ctrl_tb_intel_generic_serial_flash_interface_if_ctrl_191_ztsk5pi.sv

When I look into the file flash_ctrl_tb_intel_generic_serial_flash_interface_if_ctrl_191_ztsk5pi.sv I can see that the intel_generic_serial_flash_interface_asmiblock is being instantiated and it has the generic ENABLE_SIM_MODEL. But when I open the intel_generic_serial_flash_interface_asmiblock.sv file I can see that it doesn't have that generic.

I have searched online for the error and only found this article, that states that the problem will be solved in version 18.1 upwards:
Error (suppressible): (vopt-2732)... (intel.com)

I can't find an article mentioning the same problem for Quartus Prime Standard 19.1, which is the version I am using. I can also not find any patches or hotfixes for Standard 19.1. The exact version I am using is called 19.1.0 Build 670, which seems to be the one that is downloadable from Intel.

Does a workaround for this problem exist?

Best Regards,
Florian

FHint

4 years ago

I was able to simulate the flash by using the method explained in the linked article.

It is necessary to create a wrapper for the flash simulation model, that your vendor will (hopefully) provide.
In my case, the simulation model was only available in Verilog and the wrapper had to be in Verilog too, because of naming issues (VHDL doesn't allow for signals to end with an "_").

My wrapper asmi_sim_model.v looks like this:

`timescale 1ps/1ps

module asmi_sim_model(
  input wire clk,
  input wire qspi_pins_dclk,
  input wire qspi_pins_ncs,
  inout wire [3:0] qspi_pins_data
  );
  
  // third party flash simulation module
  <name_of_your_flash_sim_model> device_model(
    .S(qspi_pins_ncs),
    .C_(qspi_pins_dclk),
    .HOLD_DQ3(qspi_pins_data[3]),
    .DQ0(qspi_pins_data[0]),
    .DQ1(qspi_pins_data[1]),
    .Vcc('d1800),
    .Vpp_W_DQ2(qspi_pins_data[2])
  );
    
endmodule

To instantiate the wrapper in my platform designer testbench I also had to create the corresponding _hw.tcl.

The GSFI ASMI SPI interface has to be exported and connected to the asmi_sim_model wrapper. ENABLE_SIM_MODEL has to be deactivated.
It was also necessary to link all the files the flash simulation model needs in the asmi_sim_model_hw.tcl.

I hope this answer helps whoever struggles with the same problem.

Best Regards,
Florian

7 Replies

Farabi

Regular Contributor

4 years ago

Hi,

This is known issue and planned to fix in Quartus II version 21.1 std .

There is workaround to bypass this error: by manually disabling the "Enable Simulation" setting of IP to perform the gate level simulation.

"enable_simulation"	STD	PRO
TRUE	the user will need to add a wrapper module "asmi_sim_model". And instantiate a Flash Simulation model in this wrapper.	An EPCQ simulation model will be instantiated
False	ASMI connection is left unconnected	the user will need to add a wrapper module "asmi_sim_model". And instantiate a Flash Simulation model in this wrapper.

A wrapper module "asmi_sim_model" and 3rd party flash model is needed to resolve the issue.

regards,
Farabi

FHint
Occasional Contributor
4 years ago
Hello,

I am using the STD version. Does that mean I have to keep the "ENABLE_SIM_MODEL" at "true" an just add a component called "asmi_sim_model" to the Qsys system that I want to simulate? Or do I need to disable "ENABLE_SIM_MODEL" and add the component?

Best Regards,
Florian
FHint
Occasional Contributor
4 years ago
I have now tried to simulate the GSFI with "ENABLE_SIM_MODEL" disabled but the error message persists:

# ** Error (suppressible): (vsim-3584) ./../modelsim/sim/../intel_generic_serial_flash_interface_if_ctrl_191/sim/flash_ctrl_tb_intel_generic_serial_flash_interface_if_ctrl_191_qkgb6ua.sv(860): Module parameter 'ENABLE_SIM_MODEL' not found for override.
# Time: 0 ps Iteration: 0 Instance: /test_program/flash_ctrl_tb_inst/intel_generic_serial_flash_interface_top_0/qspi_inf_inst File: ./../modelsim/sim/../intel_generic_serial_flash_interface_if_ctrl_191/sim/flash_ctrl_tb_intel_generic_serial_flash_interface_if_ctrl_191_qkgb6ua.sv

It seems that not the "true" or "false" was the problem but rather the existence of the parameter itself.

Maybe I have misunderstood the solution you mentioned above. Is the wrapper meant to contain the GSFI too?

Best Regards,
Florian

Farabi
Regular Contributor
4 years ago
Hi,

If you choose simulation enable is "True" then you will need to add a wrapper module "asmi_sim_model". And instantiate a Flash Simulation model in this wrapper.

regards,
Farabi
- FHint
  Occasional Contributor
  4 years ago
  Hello,
  
  is this the solution you are referring to?
  
  1.3.2. Example: Simulating the ASMI Block in a Stratix® V Device... (intel.com)
  
  Here it says, that the "ENABLE_SIM_MODEL" parameter has to be disabled. Which way is correct?
  
  Do I need to connect the "asmi_sim_model" component to the GSFI? I guess so, because otherwise all the asmi pins are just open.
  
  Best Regards,
  Florian
  - FHint
    Occasional Contributor
    4 years ago
    I was able to simulate the flash by using the method explained in the linked article.
    
    It is necessary to create a wrapper for the flash simulation model, that your vendor will (hopefully) provide.
    In my case, the simulation model was only available in Verilog and the wrapper had to be in Verilog too, because of naming issues (VHDL doesn't allow for signals to end with an "_").
    
    My wrapper asmi_sim_model.v looks like this:
    
    `timescale 1ps/1ps module asmi_sim_model( input wire clk, input wire qspi_pins_dclk, input wire qspi_pins_ncs, inout wire [3:0] qspi_pins_data ); // third party flash simulation module <name_of_your_flash_sim_model> device_model( .S(qspi_pins_ncs), .C_(qspi_pins_dclk), .HOLD_DQ3(qspi_pins_data[3]), .DQ0(qspi_pins_data[0]), .DQ1(qspi_pins_data[1]), .Vcc('d1800), .Vpp_W_DQ2(qspi_pins_data[2]) ); endmodule
    
    To instantiate the wrapper in my platform designer testbench I also had to create the corresponding _hw.tcl.
    
    The GSFI ASMI SPI interface has to be exported and connected to the asmi_sim_model wrapper. ENABLE_SIM_MODEL has to be deactivated.
    It was also necessary to link all the files the flash simulation model needs in the asmi_sim_model_hw.tcl.
    
    I hope this answer helps whoever struggles with the same problem.
    
    Best Regards,
    Florian

Forum Discussion

Simulating the Generic Serial Flash Interface with ModelSim and Quartus 19.1

7 Replies

Recent Discussions

PCIe Enumeration Failure for CXL IP

Can't generate F-Tile Ethernet Hard IP Design Example

Agilex 7 slew rate reconfiguration

Constraints not being picked for DCFIFO

Cyclone 10 GX IBIS-AMI models