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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Simulating RS232 UART IP Core in VHDL

Hello, I am currently working on a FPGA design containing a UART interface and have choosen the Intel RS232 UART IP Core from the University Program to use for this. I would like to simulate the ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi Florian,


I try with other device families. Simulation of UART RS232 IP generated in VHDL works fine in those device families. I think this legacy ip not being actively maintained for newly device family.


FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi Sheng,

thank you for the information and the effort you've put into it!
How can I change the family and device of a Qsys system in the Platform Designer?
I can only find these when opening the .qsys file with a text editor and not when opening it with the Platform Designer.
Except for the instanced VHDL component mentioned above the testbench is not connected to a project.

Best Regards,
Florian