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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Simulating RS232 UART IP Core in VHDL

Hello, I am currently working on a FPGA design containing a UART interface and have choosen the Intel RS232 UART IP Core from the University Program to use for this. I would like to simulate the ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi Florian,

I try with other IPs generated in VHDL can be simulated properly but UART RS232 IP (VHDL) cannot. I found this previous KDB https://www.intel.com/content/www/us/en/support/programmable/articles/000080465.html at which RS232 UART IP generated in VHDL can't be simulated properly because of simulation files missing. Workaround is select Verilog while generating the RS232 UART IP. Feedbacks from design team for this previous KDB are:

  • To update issue exist in 19.1 Std and well, I am creating a KDB to educate customer with workaround
  • This is a legacy IP that is not being actively maintained

(Sorry for any inconvenience)

Below attached a zip UART RS232 IP design file under Verilog language for your reference. Tested with no component "unsaved 1.0" wasn't found error.

Thanks,

Best Regards,

Sheng