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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Simulating RS232 UART IP Core in VHDL

Hello, I am currently working on a FPGA design containing a UART interface and have choosen the Intel RS232 UART IP Core from the University Program to use for this. I would like to simulate the ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

Seems like modelsim can't find that module.

You have to manually add the .qip and .sip files after generating the IP core.

The .qip will be located in <generation_directory>/synthesis/.qip

The .sip will be located in <generation_directory>/simulation/.sip

You can also try on Modelsim Simulation Setup Script (msim_setup.tcl) in testbench/Mentor. Refer to manual here or video here.

**Note: This feature is available in the Intel Quartus Prime Pro Edition software for all devices.
This feature is available in the Intel Quartus Prime Standard Edition software for only Intel Arria 10 devices.

Best regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi Sheng,

thank you for the quick answer!

How do I generate the RS232 UART IP Core solely? I have added the component in Platform Designer, but I can only generate the whole subsystem including the IP Core and not the IP Core only. Therefore the synthesis and simulation folders for the IP Core are not generated.

Regarding the IP Core only this folder is created:

<subsystem_name>\altera_up_avalon_rs232_171\synth

which contains some Verilog and VHDL files. When generating the subsystem the "Simulation" box was ticked and all language options were set to "VHDL".

Is there a way to generate the RS232 UART IP Core solely?

Best regards,
Florian