Simulating custom DDR controller with ALTMEMPHY using ModelSim-Altera Starter edition

Hi,

Here are some Verilog code snips that are from my working design. It simulates in Modelsim and works on a NEEK development board (Cyclone III).

DDR mphy(.pll_ref_clk(osc_clk), .global_reset_n(reset_n),

.soft_reset_n(1'b1),

.ctl_dqs_burst(ctl_dqs_burst), .ctl_wdata_valid(ctl_wdata_valid),

.ctl_wdata(ctl_wdata), .ctl_dm(ctl_dm),

.ctl_addr(ctl_addr), .ctl_ba(ctl_ba), .ctl_cas_n(ctl_cas_n),

.ctl_cke(ctl_cke), .ctl_cs_n(ctl_cs_n), .ctl_odt(ctl_odt),

.ctl_ras_n(ctl_ras_n), .ctl_we_n(ctl_we_n), .ctl_rst_n(reset_n),

.ctl_mem_clk_disable(ctl_mem_clk_disable),

.ctl_doing_rd(ctl_doing_rd),

.ctl_cal_req(ctl_cal_req),

.ctl_cal_byte_lane_sel_n(ctl_cal_byte_lane_sel_n),

.ctl_clk(ctl_clk), .ctl_reset_n(ctl_reset_n),

.ctl_wlat(ctl_wlat), .ctl_rdata(ctl_rdata),

.ctl_rdata_valid(ctl_rdata_valid), .ctl_rlat(ctl_rlat),

.ctl_cal_success(ctl_cal_success), .ctl_cal_fail(ctl_cal_fail),

.ctl_cal_warning(ctl_cal_warning),

//

.dbg_clk(ctl_clk), .dbg_reset_n(ctl_reset_n), .dbg_addr(13'h0000),

.dbg_wr(1'b0), .dbg_rd(1'b0), .dbg_cs(1'b0),

.dbg_wr_data(32'h00000000), .dbg_rd_data(dbg_rd_data),

.dbg_waitrequest(dbg_waitrequest), .reset_request_n(reset_request_n),

//

.mem_addr(ddr_addr), .mem_ba(ddr_ba), .mem_cas_n(ddr_cas_n),

.mem_cke(ddr_cke), .mem_cs_n(ddr_cs_n), .mem_dm(ddr_dm),

.mem_odt(mem_odt), .mem_ras_n(ddr_ras_n), .mem_we_n(ddr_we_n),

.mem_reset_n(mem_reset_n),

.mem_clk(ddr_clk), .mem_clk_n(ddr_clk_n),

.mem_dq(ddr_dq), .mem_dqs(ddr_dqs), .mem_dqs_n(),

//

.aux_half_rate_clk(aux_half_rate_clk),

.aux_full_rate_clk(aux_full_rate_clk));

The key to getting the ALTMEMPHY started is the initial state of inputs from the controller. The inputs must be in the initial state until "ctl_cal_success" is true.

ctl_dqs_burst <= 2'b00;

ctl_wdata_valid <= 2'b00;

ctl_dm <= 4'b1111;

ctl_addr <= 13'h0000;

ctl_ba <= 2'b00;

ctl_cke <= 1'b1;

{ctl_cs_n, ctl_ras_n, ctl_cas_n, ctl_we_n} <= 4'b1111;

ctl_mem_clk_disable <= 1'b0;

ctl_doing_rd <= 2'b00;

ctl_cal_req <= 1'b0;

ctl_cal_byte_lane_sel_n <= 2'b00;

I believe the important thing is to initialize inputs to their inactive states until the calibration process is complete (even when skipping calibration).

It's been a while since I was working on this. So, I hope I didn't miss anything.

Ken