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Altera_Forum
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15 years ago

Simulate QDR Controler UniPHY

Hi all, I generated a QDR II Controller with UniPHY. After compiled the sources generated by mega wizard (verilog and systemVerilog), the top (vhdl) and the testbench (vhdl), I tried to simulat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi all,

I finally resolve the errors !

The error was due to the VHDL altera libraries for this controller. I used now the verilog libraries and it works fine.

I reported to Altera.