Forum Discussion
Altera_Forum
Honored Contributor
17 years agoHi Jake,
Thanks for your comments! I checked Micron's parameter setting file (ddr2_parameters.vh) for the ddr2 simulation model, but didn't see any problems on that. Also, I run the following command in modelsim to compile this ddr2 model. vlog -work auk_ddr_user_lib +define+sg37E+x16+MAX_MEM ../ddr2.v I think I was using the correct speed grade for simulation. The timing violations are everywhere for each ddr2 command issued to the memory, such as ACT, PCH, WR, RD... What should I do? Xin