Honored Contributor
Honored ContributorSorry, just wanna update my simulation progress!
I modified the test bench (example_top_tb.vhd) that is provided together with the DDR2 controller, by setting "reset_n" signal low at the beginning 12 clock cycles (previously, it was high for 6 clock cycles, followed by 6 clock cycles' low, then back to high afterwards). The simulation passed without previous ERROR on "Load Mode Failure". However, the results showed a lot of timing violation problems, for example: ERROR: tRFC violation during Write. ERROR: tCK(avg) minimum violation by 6.000000 ps. ERROR: tRP violation during Activate to bank 4. ... ... How could I avoid these violations? Thanks, Xin
