Forum Discussion
CheepinC_altera
Regular Contributor
6 years agoHi,
To ensure we are on the same page, just would like to clarify if you are using HPS TSE IP or if you are using normal FPGA TSE IP? If you are using normal FPGA TSE IP, just wonder if you have had a chance to test enabling the SGMII_ENA register bit. You may refer to section 5.2.5. If_Mode Register (Word Offset 0x14) in the TSE user guide forfurther details.
Thank you.
- JLee256 years ago
Contributor
Hi CheePin,
Thank you!
I will check the FPGA TSE IP core mode register as mentioned.
BRs,
Johnson