Simple DMA Controller Mystery

I have implemented a qsys design with pcie_hard_ip, Altera's DMA controller and my custom Avalon component as a slave to the DMA controller. For testing, my custom component presents a constant 32-bit value on the readdata lines. My component implements readdatavalid (set to 1) and waitrequest (set to 0) to When I program the DMA controller with a byte count of 4, tell it not to increment the source address, and set the GO bit, I get one 32-bit word transferred to my target (PC Host) and DMA controller status bits DONE and LEN set to 1. As it should be. But, if I set the byte count to > 4, I only get one word transferred, the DMA controller status indicates BUSY and the length register is 4. At this point, I have to reload the sof file and reboot the PC before any DMA controller commands have an effect again.

Looking at the read line on the o-scope while I run the above, it's high for 4 clocks, in both the count=4 and count > 4 cases. Seems it should be high for just one clock to read a 32-bit word... one byte width enforced somewhere? byteenable bits from master are all high.

Specs: Stratix IV, Quartus 12.0, DMA bursting enabled, controller-supported data types include 32-bit word. x4 PCIe, 125MHz app clk, reconfig block in place, running on target hardware, not doing simulation. Hardware works with Altera's chaining DMA example.

To summarize:

1 - Why can't I transfer more than one 32-bit word?

2 - Why 4 read cycles for one 32-bit word?

Hopefully there's enough info here to be of use. Does anybody have any ideas why this isn't working?

Thanks,

Tom