signed to unsigned

I would suggest to open a Service Request for this issue. This way Altera can fix the Simulink simulation in a later version.

To simulate VHDL just add the Testbench block to your model and open it. There you can start a VHDL simulation in ModelSim to compare the results to the Simulink simulation.

By the way, I also had to discover lately the hard way a difference between the Simulink simulation and the real FPGA behavior. If you ever use a dualport RAM with MLAB's and you read from and write to the same address be prepared for a surprise. The Simulink simulation does a read before write behavior but the generated VHDL code does a write before read.